1. Field of the Invention
The embodiments described herein relate generally to video processing circuits and methods, and more particularly, to circuits and methods that process multiple input and output video timing formats.
2. Description of Related Art
Digital video timing is characterized by several synchronization signals, including the pixel clock, the horizontal synchronization (HSync), the vertical synchronization (VSync), the pixel/data enable (DE), and the field enable signals. The pixel clock signal indicates when a synchronization, control, and data signals should be sampled by the digital system. The pixel clock rate determines the number of pixel clocks per synchronization signal period (ie. per VSync period and per Hsync period). The horizontal synchronization signal (HSync) indicates the start and end of a horizontal line of pixels. The vertical synchronization signal (VSync) indicates the start and end of a vertical field or frame of lines. The pixel/data Enable (DE) signal indicates when pixels within a horizontal line are active (accompanied by valid data). The number of active (i.e. DE asserted) pixel clocks per frame defines the active resolution of the video format. The field enable signal indicates whether the current interlaced field is Field 0 (low) or Field 1 (high).
Synchronization is defined as maintaining, on average, a constant integer ratio of input Vsync signals to output Vsync signals over an interval of time. For example, a system may be required to maintain 5 output Vsync signals on average for every 3 input Vsync signals received.
These synchronization signals define the timing parameters of many video formats such as standard-definition and high-definition TV. One important function in an electronic video processing system is to synchronize the input and output video format timing, each having separate pixel clocks and corresponding clock rates, respectively.
A format conversion is often needed between the video input and the video output rates that involves changing the number of pixel clocks, the number of active pixels, and/or the number of Hsync samples per field or frame and the position of active pixel data within that field or frame between an input format and an output format.
For example, if the input video format is a North American standard definition video channel, it is formatted using 720 active pixels per 480 interlaced active video lines running at a 13.5 MHz pixel clock frequency. A common practice is to convert this video to a high-definition video format that is defined using 1920 active pixels per 1080 progressive active video lines running at a 150 MHz pixel clock frequency.
An important synchronization signal is the vertical frame rate, also defined as the period of the VSync signal. The vertical frame rate is standardized in North America for broadcast and for wire line transmission to 60 frames per second, although in other jurisdictions other vertical frame rates may be utilized. The VSync signal is used to lock the output frame rate to the input frame rate in systems where no frame-rate conversion is needed. Most often in digital display systems a constant number of pixel clocks per VSync period are required by the display electronics and/or the standard formats' specification.
Modern video processing circuits support an increasingly large array of input and output video timing formats. These formats range from the legacy standard-definition television video (SDTV) up to and beyond the modern ultra-high definition television (UHDTV). The possible range of video synchronization timing varies between these formats from the original 13.5 MHz (SDTV) timing to more than 350 MHz (UHDTV). The difference in synchronization signal intervals and/or pixel clock frequencies (1/period) between existing video timing formats can exceed a ratio of 25:1. Classic pixel clock synthesis and control systems implemented to operate across this range are often costly and require multiple discrete circuits to span the full required range. Moreover, with the advent of new display technologies and new applications for existing technologies, the requirements in terms of adaptability and flexibility of operation for a video processing circuit are expected to increase.
Video input and output formats change frequently during the lifespan of a video display device or application. For example, the latest Blu-ray Disc technical specification supports over 12 different video formats. As another example, modern digital televisions (DTVs) support resolutions that span from SDTV to UHDTV. Consumers expect to switch channels and have the electronic system automatically detect the format change, adjust all internal synchronization signals, and display a perfect picture without any image distortion. For example, electronic display systems typically assume that the synchronization signaling they receive is uninterrupted and maintain a standard video timing format. Classic video synchronization methods do not implement the control that presents a complete spectrum of display output choices to the system in response to input format switching. As a result, classic methods may simply shut off the display system or present it with non-standard (or invalid) video timing that will result in visibly displayed picture distortion.
What is needed is a video processing circuit that can process signals throughout the wide range of available video formats, maintaining uniform quality standards and seamlessly transitioning from a first video format (input) to a second video format (output). In addition, a system is needed to filter or average the input timing variations in the period of the received pixel clock and synchronization signals such that the generated output timing can adapt to period and phase changes in the input timing while rejecting high frequency change in the input timing.